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2022-04-05Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* fix vss-win32 compilation with clang++ * update Coverity model * add measurement calculation to amd-memory-encryption docs # gpg: Signature made Tue 05 Apr 2022 09:42:59 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "[email protected]" # gpg: Good signature from "Paolo Bonzini <[email protected]>" [full] # gpg: aka "Paolo Bonzini <[email protected]>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: docs/system/i386: Add measurement calculation details to amd-memory-encryption qga/vss-win32: fix compilation with clang++ coverity: update model for latest tools Signed-off-by: Peter Maydell <[email protected]>
2022-04-05docs/system/i386: Add measurement calculation details to amd-memory-encryptionDov Murik
Add a section explaining how the Guest Owner should calculate the expected guest launch measurement for SEV and SEV-ES. Also update the name and links to the SEV API Spec document. Signed-off-by: Dov Murik <[email protected]> Suggested-by: Daniel P. Berrangé <[email protected]> Reviewed-by: Dr. David Alan Gilbert <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2022-04-05docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.Pavel Pisa
Signed-off-by: Pavel Pisa <[email protected]> Reviewed-by: Francisco Iglesias <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2022-03-03Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging Fifth RISC-V PR for QEMU 7.0 * Fixup checks for ext_zb[abcs] * Add AIA support for virt machine * Increase maximum number of CPUs in virt machine * Fixup OpenTitan SPI address * Add support for zfinx, zdinx and zhinx{min} extensions # gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <[email protected]>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20220303: target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv: add support for zhinx/zhinxmin target/riscv: add support for zdinx target/riscv: add support for zfinx target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} hw: riscv: opentitan: fixup SPI addresses hw/riscv: virt: Increase maximum number of allowed CPUs docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Add optional AIA IMSIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine target/riscv: fix inverted checks for ext_zb[abcs] Signed-off-by: Peter Maydell <[email protected]>
2022-03-03docs/system: riscv: Document AIA options for virt machineAnup Patel
We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel <[email protected]> Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Frank Chang <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
2022-03-02target/arm: Implement FEAT_LPA2Richard Henderson
This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 4k or 16k pages. This introduces the DS bit to TCR_ELx, which is RES0 unless the page size is enabled and supports LPA2, resulting in the effective value of DS for a given table walk. The DS bit changes the format of the page table descriptor slightly, moving the PS field out to TCR so that all pages have the same sharability and repurposing those bits of the page table descriptor for the highest bits of the output address. Do not yet enable FEAT_LPA2; we need extra plumbing to avoid tickling an old kernel bug. Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2022-03-02target/arm: Implement FEAT_LPARichard Henderson
This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 64k pages. The only thing left at this point is to handle the extra bits in the TTBR and in the table descriptors. Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't mask out the high bits when writing to those registers, so no changes are required there. Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2022-03-02target/arm: Implement FEAT_LVARichard Henderson
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2022-02-28Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell
into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <[email protected]>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <[email protected]>
2022-02-26arm: Remove swift-bmc machineJoel Stanley
It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]> Signed-off-by: Cédric Le Goater <[email protected]>
2022-02-23Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange-gitlab/tags/misc-next-pull-request' into staging This misc series of changes: - Improves documentation of SSH fingerprint checking - Fixes SHA256 fingerprints with non-blockdev usage - Blocks the clone3, setns, unshare & execveat syscalls with seccomp - Blocks process spawning via clone syscall, but allows threads, with seccomp - Takes over seccomp maintainer role - Expands firmware descriptor spec to allow flash without NVRAM # gpg: Signature made Thu 17 Feb 2022 11:57:13 GMT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <[email protected]>" [full] # gpg: aka "Daniel P. Berrange <[email protected]>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange-gitlab/tags/misc-next-pull-request: docs: expand firmware descriptor to allow flash without NVRAM MAINTAINERS: take over seccomp from Eduardo Otubo seccomp: block setns, unshare and execveat syscalls seccomp: block use of clone3 syscall seccomp: fix blocking of process spawning seccomp: add unit test for seccomp filtering seccomp: allow action to be customized per syscall block: print the server key type and fingerprint on failure block: support sha256 fingerprint with pre-blockdev options block: better document SSH host key fingerprint checking Signed-off-by: Peter Maydell <[email protected]>
2022-02-21hw/arm: add initial mori-bmc boardPatrick Venture
This is the BMC attached to the OpenBMC Mori board. Signed-off-by: Patrick Venture <[email protected]> Reviewed-by: Chris Rauer <[email protected]> Reviewed-by: Ilkyun Choi <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
2022-02-16block: better document SSH host key fingerprint checkingDaniel P. Berrangé
The docs still illustrate host key fingerprint checking using the old md5 hashes which are considered insecure and obsolete. Change it to illustrate using a sha256 hash. Also show how to extract the hash value from the known_hosts file. Reviewed-by: Hanna Reitz <[email protected]> Signed-off-by: Daniel P. Berrangé <[email protected]>
2022-02-16docs/system: riscv: Update description of CPUYu Li
Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=true` or `h=true` is also no longer required. Signed-off-by: Yu Li <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
2022-02-09docs: rstfy confidential guest documentationCornelia Huck
Also rstfy the documentation for AMD SEV, and link it. The documentation for PEF had been merged into the pseries doc, fix the reference. Signed-off-by: Cornelia Huck <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-Id: <[email protected]> Signed-off-by: Cédric Le Goater <[email protected]>
2022-01-20docs/can: convert to restructuredTextLucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Lucas Ramage <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> [PMM: Move to docs/system/devices/ rather than top-level; fix a pre-existing typo in passing] Signed-off-by: Peter Maydell <[email protected]>
2022-01-20hw/arm/virt: KVM: Enable PAuth when supported by the hostMarc Zyngier
Add basic support for Pointer Authentication when running a KVM guest and that the host supports it, loosely based on the SVE support. Although the feature is enabled by default when the host advertises it, it is possible to disable it by setting the 'pauth=off' CPU property. The 'pauth' comment is removed from cpu-features.rst, as it is now common to both TCG and KVM. Tested on an Apple M1 running 5.16-rc6. Cc: Eric Auger <[email protected]> Cc: Richard Henderson <[email protected]> Cc: Peter Maydell <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] [PMM: fixed indentation] Signed-off-by: Peter Maydell <[email protected]>
2022-01-19Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-7.0-180122-2' ↵Peter Maydell
into staging Various testing and other misc updates: - fix compiler warnings with ui and sdl - update QXL/spice dependancy - skip I/O tests on Alpine - update fedora image to latest version - integrate lcitool and regenerate docker images - favour CONFIG_LINUX_USER over CONFIG_LINUX - add libfuse3 dependencies to docker images - add dtb-kaslr-seed control knob to virt machine - fix build breakage from HMP update - update docs for C standard and suffix usage - add more logging for debugging user hole finding - expand reserve for brk() for static 64 bit programs - fix bug with linux-user hole calculation - avoid affecting flags when printing results in float tests - add float reference files for ppc64 - update FreeBSD to 12.3 - add bison dependancy to tricore images # gpg: Signature made Tue 18 Jan 2022 16:47:42 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <[email protected]>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-for-7.0-180122-2: (31 commits) docker: include bison in debian-tricore-cross FreeBSD: Upgrade to 12.3 release test/tcg/ppc64le: Add float reference files tests/tcg/multiarch: Read fp flags before printf linux-user: don't adjust base of found hole linux-user/elfload: add extra logging for hole finding linux-user: expand reserved brk space for 64bit guests docs/devel: more documentation on the use of suffixes docs/devel: update C standard to C11 monitor: move x-query-profile into accel/tcg to fix build hw/arm: add control knob to disable kaslr_seed via DTB tests/docker: add libfuse3 development headers tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX tests/docker: auto-generate alpine.docker with lcitool tests/docker: fully expand the alpine package list tests/docker: fix sorting of alpine image package lists tests/docker: updates to alpine package list .gitlab-ci.d/cirrus: auto-generate variables with lcitool tests/docker: remove ubuntu.docker container tests/docker: auto-generate opensuse-leap.docker with lcitool ... Signed-off-by: Peter Maydell <[email protected]>
2022-01-18hw/arm: add control knob to disable kaslr_seed via DTBAlex Bennée
Generally a guest needs an external source of randomness to properly enable things like address space randomisation. However in a trusted boot environment where the firmware will cryptographically verify components having random data in the DTB will cause verification to fail. Add a control knob so we can prevent this being added to the system DTB. Signed-off-by: Alex Bennée <[email protected]> Tested-by: Heinrich Schuchardt <[email protected]> Acked-by: Ilias Apalodimas <[email protected]> Acked-by: Jerome Forissier <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Message-Id: <[email protected]>
2022-01-18Link new ppc-spapr-uv-hcalls.rst to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-Id: <a24d2c260442e44aa99d4c18b1717f2f4a73529a.1642446876.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2022-01-18Link new ppc-spapr-hotplug.rst file to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-Id: <e54aad58e3cfbd96647430d33cdb59fd87d199b0.1641995058.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2022-01-12docs: Clarifications and formatting changes in ppc docs.Leonardo Garcia
Signed-off-by: Leonardo Garcia <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]> Message-Id: <3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2022-01-12docs/system/ppc: Merge the PEF information into the pseries pageThomas Huth
The Protected Execution Facility is only available with the pseries machine, so let's merge the old ASCII text into the new RST file now. Signed-off-by: Thomas Huth <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-Id: <[email protected]> Signed-off-by: Cédric Le Goater <[email protected]>
2021-12-17Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into stagingRichard Henderson
ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) # gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <[email protected]>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits) ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Drop the "num-phbs" property ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Introduce a "chip" property under PHB3 PPC64/TCG: Implement 'rfebb' instruction target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: enable PMU instruction count target/ppc: enable PMU counter overflow with cycle events target/ppc: PMU: update counters on MMCR1 write target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU basic cycle count for pseries TCG ... Signed-off-by: Richard Henderson <[email protected]>
2021-12-17Link new ppc-spapr-hcalls.rst file to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-Id: <7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2021-12-17docs: Introducing pseries documentation.Leonardo Garcia
The purpose of this document is to substitute the content currently available in the QEMU wiki at [0]. This initial version does contain some additional content as well. Whenever this documentation gets upstream and is reflected in [1], the QEMU wiki will be edited to point to this documentation, so that we only need to keep it updated in one place. 0. https://wiki.qemu.org/Documentation/Platforms/POWER 1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html Signed-off-by: Leonardo Garcia <[email protected]> Reviewed-by: David Gibson <[email protected]> Message-Id: <66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2021-12-17docs/system/ppc/powernv.rst: document KVM support statusDaniel Henrique Barboza
Put in a more accessible place the reasoning behind our decision to officially drop KVM support in the powernv machine. Signed-off-by: Daniel Henrique Barboza <[email protected]> Message-Id: <[email protected]> Signed-off-by: Cédric Le Goater <[email protected]>
2021-12-17docs: Minor updates on the powernv documentation.Leonardo Garcia
Signed-off-by: Leonardo Garcia <[email protected]> [ clg: replaced Power9 by POWER9 ] Message-Id: <c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <[email protected]>
2021-12-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* improve compatibility for macOS scripts/entitlement.sh (Evan) * add support for KVM_GUESTDBG_BLOCKIRQ (Maxim) * update linux-headers to Linux 5.16 (myself) * configure cleanups (myself) * lsi53c895a assertion failure fix (Philippe) * fix incorrect description for die-id (Yanan) * support for NUMA in SGX enclave memory (Yang Zhong) # gpg: Signature made Wed 15 Dec 2021 02:49:44 AM PST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "[email protected]" # gpg: Good signature from "Paolo Bonzini <[email protected]>" [unknown] # gpg: aka "Paolo Bonzini <[email protected]>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: configure: remove dead variables doc: Add the SGX numa description numa: Support SGX numa in the monitor and Libvirt interfaces numa: Enable numa for SGX EPC sections kvm: add support for KVM_GUESTDBG_BLOCKIRQ gdbstub, kvm: let KVM report supported singlestep flags gdbstub: reject unsupported flags in handle_set_qemu_sstep linux-headers: update to 5.16-rc1 virtio-gpu: do not byteswap padding scripts/entitlement.sh: Use backward-compatible cp flags qapi/machine.json: Fix incorrect description for die-id tests/qtest: Add fuzz-lsi53c895a-test hw/scsi/lsi53c895a: Do not abort when DMA requested and no data queued Signed-off-by: Richard Henderson <[email protected]>
2021-12-15docs: aspeed: ADC is now modelledJoel Stanley
Move it to the supported list. Signed-off-by: Joel Stanley <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2021-12-15docs: aspeed: Give an example of booting a kernelJoel Stanley
A common use case for the ASPEED machine is to boot a Linux kernel. Provide a full example command line. Reviewed-by: Cédric Le Goater <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2021-12-15docs: aspeed: Update OpenBMC image URLJoel Stanley
This is the latest URL for the OpenBMC CI. The old URL still works, but redirects. Reviewed-by: Cédric Le Goater <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2021-12-15docs: aspeed: Add new boardsJoel Stanley
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be removed in v7.0. Signed-off-by: Joel Stanley <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
2021-12-10doc: Add the SGX numa descriptionYang Zhong
Add the SGX numa reference command and how to check if SGX numa is support or not with multiple EPC sections. Signed-off-by: Yang Zhong <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2021-11-22docs: Render binary names as monospaced textPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Message-Id: <[email protected]> Reviewed-by: Darren Kenny <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
2021-11-22docs: Drop deprecated 'props' from object-addRao, Lei
In commit 5024340745 "qapi/qom: Drop deprecated 'props' from object-add" (v6.0.0), we also should update documents. Signed-off-by: Lei Rao <[email protected]> Message-Id: <[email protected]> Reviewed-by: Markus Armbruster <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
2021-11-22Fix some typos in documentation (found by codespell)Stefan Weil
Signed-off-by: Stefan Weil <[email protected]> Message-Id: <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> [thuth: "what's" --> "what is" as suggested by philmd] Signed-off-by: Thomas Huth <[email protected]>
2021-11-19Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
Bugfixes for 6.2. # gpg: Signature made Fri 19 Nov 2021 10:33:29 AM CET # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "[email protected]" # gpg: Good signature from "Paolo Bonzini <[email protected]>" [full] # gpg: aka "Paolo Bonzini <[email protected]>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: chardev/wctable: don't free the instance in wctablet_chr_finalize meson.build: Support ncurses on MacOS and OpenBSD docs: Spell QEMU all caps qtest/am53c974-test: add test for reset before transfer esp: ensure that async_len is reset to 0 during esp_hard_reset() nvmm: Fix support for stable version meson: fix botched compile check conversions Signed-off-by: Richard Henderson <[email protected]>
2021-11-19docs: Spell QEMU all capsPhilippe Mathieu-Daudé
Replace Qemu -> QEMU. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Darren Kenny <[email protected]> Reviewed-by: Markus Armbruster <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2021-11-19hw/nvme: change nvme-ns 'shared' defaultKlaus Jensen
Change namespaces to be shared namespaces by default (parameter shared=on). Keep shared=off for older machine types. Reviewed-by: Keith Busch <[email protected]> Signed-off-by: Klaus Jensen <[email protected]>
2021-11-08tests/acceptance: rename tests acceptance to tests avocadoWillian Rampazzo
In the discussion about renaming the `tests/acceptance` [1], the conclusion was that the folders inside `tests` are related to the framework running the tests and not directly related to the type of the tests. This changes the folder to `tests/avocado` and adjusts the MAKEFILE, the CI related files and the documentation. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-05/msg06553.html Reviewed-by: Niek Linnenbank <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Tested-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Willian Rampazzo <[email protected]> Message-Id: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
2021-11-08docs: (further) remove non-reference uses of single backticksJohn Snow
The series rotted already. Here's the new changes. Signed-off-by: John Snow <[email protected]> Reviewed-by: Damien Hedde <[email protected]> [ extra backticks fixes ] Signed-off-by: Marc-André Lureau <[email protected]> Message-Id: <[email protected]>
2021-11-08docs: remove non-reference uses of single backticksJohn Snow
The single backtick markup in ReST is the "default role". Currently, Sphinx's default role is called "content". Sphinx suggests you can use the "Any" role instead to turn any single-backtick enclosed item into a cross-reference. This is useful for things like autodoc for Python docstrings, where it's often nicer to reference other types with `foo` instead of the more laborious :py:meth:`foo`. It's also useful in multi-domain cases to easily reference definitions from other Sphinx domains, such as referencing C code definitions from outside of kerneldoc comments. Before we do that, though, we'll need to turn all existing usages of the "content" role to inline verbatim markup wherever it does not correctly resolve into a cross-refernece by using double backticks instead. Signed-off-by: John Snow <[email protected]> Reviewed-by: Eduardo Habkost <[email protected]> Reviewed-by: Alexander Bulekov <[email protected]> Message-Id: <[email protected]>
2021-10-20docs: Add documentation for vhost based RNG implementationMathieu Poirier
Add description and example for the vhost-user based RNG implementation. Signed-off-by: Mathieu Poirier <[email protected]> Message-Id: <[email protected]> Reviewed-by: Michael S. Tsirkin <[email protected]> Signed-off-by: Michael S. Tsirkin <[email protected]>
2021-10-05i386: docs: Briefly describe KVM PV featuresVitaly Kuznetsov
KVM PV features don't seem to be documented anywhere, in particular, the fact that some of the features are enabled by default and some are not can only be figured out from the code. Signed-off-by: Vitaly Kuznetsov <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
2021-09-30Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20210930' into staging target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5.2 * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices * gdbstub related code cleanups * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML * Use _init vs _new convention in bus creation function names * sabrelite: Connect SPI flash CS line to GPIO3_19 # gpg: Signature made Thu 30 Sep 2021 16:11:20 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "[email protected]" # gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits) hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 ide: Rename ide_bus_new() to ide_bus_init() qbus: Rename qbus_create() to qbus_new() qbus: Rename qbus_create_inplace() to qbus_init() pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML target/arm: Move gdbstub related code out of helper.c target/arm: Fix coding style issues in gdbstub code in helper.c configs: Don't include 32-bit-only GDB XML in aarch64 linux configs docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage hw/arm: xlnx-zcu102: Add Xilinx eFUSE device hw/arm: xlnx-zcu102: Add Xilinx BBRAM device hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device hw/nvram: Introduce Xilinx battery-backed ram hw/nvram: Introduce Xilinx ZynqMP eFuse device hw/nvram: Introduce Xilinx Versal eFuse device hw/nvram: Introduce Xilinx eFuse QOM ... Signed-off-by: Peter Maydell <[email protected]>
2021-09-30Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * SGX implementation for x86 * Miscellaneous bugfixes * Fix dependencies from ROMs to qtests # gpg: Signature made Thu 30 Sep 2021 14:30:35 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "[email protected]" # gpg: Good signature from "Paolo Bonzini <[email protected]>" [full] # gpg: aka "Paolo Bonzini <[email protected]>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (33 commits) meson_options.txt: Switch the default value for the vnc option to 'auto' build-sys: add HAVE_IPPROTO_MPTCP memory: Add tracepoint for dirty sync memory: Name all the memory listeners target/i386: Fix memory leak in sev_read_file_base64() tests: qtest: bios-tables-test depends on the unpacked edk2 ROMs meson: unpack edk2 firmware even if --disable-blobs target/i386: Add the query-sgx-capabilities QMP command target/i386: Add HMP and QMP interfaces for SGX docs/system: Add SGX documentation to the system manual sgx-epc: Add the fill_device_info() callback support i440fx: Add support for SGX EPC q35: Add support for SGX EPC i386: acpi: Add SGX EPC entry to ACPI tables i386/pc: Add e820 entry for SGX EPC section(s) hw/i386/pc: Account for SGX EPC sections when calculating device memory hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Adjust min CPUID level to 0x12 when SGX is enabled i386: Propagate SGX CPUID sub-leafs to KVM i386: kvm: Add support for exposing PROVISIONKEY to guest ... Signed-off-by: Peter Maydell <[email protected]>
2021-09-30docs/system: Add SGX documentation to the system manualSean Christopherson
Signed-off-by: Sean Christopherson <[email protected]> Signed-off-by: Yang Zhong <[email protected]> Message-Id: <[email protected]> [Convert to reStructuredText, and adopt the standard === --- ~~~ headings suggested for example by Linux. - Paolo] Signed-off-by: Paolo Bonzini <[email protected]>
2021-09-30docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE UsageTong Ho
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board document. Signed-off-by: Tong Ho <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
2021-09-29docs/system: ppc: Update the URL for OpenPOWER firmware imagesCédric Le Goater
This also fixes a small skiboot/skiroot typo and removes the links to the specific POWER8 and POWER9 images since the firmware images can be used to run all machines. Signed-off-by: Cédric Le Goater <[email protected]> Message-Id: <[email protected]> Reviewed-by: Greg Kurz <[email protected]> Signed-off-by: David Gibson <[email protected]>
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