add register test

4 files changed, 316 insertions, 0 deletions

diff --git a/register_test/cmd.txt b/register_test/cmd.txt
new file mode 100644
index 0000000..289de1f
--- /dev/null
+++ b/register_test/cmd.txt
@@ -0,0 +1,15 @@
+#set path
+cd ~/bf-sde-9.0.0
+. ~/tools/set_sde.bash
+
+#tty1
+~/tools/p4_build.sh  ~/labs/register_test/p_register.p4
+sudo $SDE_INSTALL/bin/veth_setup.sh
+./run_tofino_model.sh -p p_register
+
+#tty2
+./run_switchd.sh -p p_register
+
+#tty3 change send.py, then perform it, and see the log in tty1
+sudo ./send.py
+
diff --git a/register_test/p_register.p4 b/register_test/p_register.p4
new file mode 100644
index 0000000..690410e
--- /dev/null
+++ b/register_test/p_register.p4
@@ -0,0 +1,252 @@
+/* -*- P4_16 -*- */
+
+#include <core.p4>
+#include <tna.p4>
+
+/*************************************************************************
+ ************* C O N S T A N T S    A N D   T Y P E S  *******************
+**************************************************************************/
+
+/*************************************************************************
+ ***********************  H E A D E R S  *********************************
+ *************************************************************************/
+
+/*  Define all the headers the program will recognize             */
+/*  The actual sets of headers processed by each gress can differ */
+
+/* Standard ethernet header */
+header ethernet_h {
+    bit<48>   dst_addr;
+    bit<48>   src_addr;
+    bit<16>   ether_type;
+}
+
+header vlan_tag_h {
+    bit<3>   pcp;
+    bit<1>   cfi;
+    bit<12>  vid;
+    bit<16>  ether_type;
+}
+
+header ipv4_h {
+    bit<4>   version;
+    bit<4>   ihl;
+    bit<8>   diffserv;
+    bit<16>  total_len;
+    bit<16>  identification;
+    bit<3>   flags;
+    bit<13>  frag_offset;
+    bit<8>   ttl;
+    bit<8>   protocol;
+    bit<16>  hdr_checksum;
+    bit<32>  src_addr;
+    bit<32>  dst_addr;
+}
+
+header test_reg_h {
+    bit<32>   tna_reg_name;
+    bit<8>    op;
+    bit<16>   opcode;
+    bit<24>   reg;
+    bit<8>    reg_choice;
+    bit<8>    reg_index;
+    bit<16>   data;
+}
+
+/*************************************************************************
+ **************  I N G R E S S   P R O C E S S I N G   *******************
+ *************************************************************************/
+ 
+    /***********************  H E A D E R S  ************************/
+
+struct my_ingress_headers_t {
+    ethernet_h   ethernet;
+    test_reg_h   reg;
+}
+
+    /******  G L O B A L   I N G R E S S   M E T A D A T A  *********/
+
+struct my_ingress_metadata_t {
+}
+
+    /***********************  P A R S E R  **************************/
+parser IngressParser(packet_in        pkt,
+    /* User */    
+    out my_ingress_headers_t          hdr,
+    out my_ingress_metadata_t         meta,
+    /* Intrinsic */
+    out ingress_intrinsic_metadata_t  ig_intr_md)
+{
+    /* This is a mandatory state, required by Tofino Architecture */
+     state start {
+        pkt.extract(ig_intr_md);
+        pkt.advance(PORT_METADATA_SIZE);
+        transition parse_ethernet;
+    }
+
+    state parse_ethernet {
+        pkt.extract(hdr.ethernet); 
+        transition select(hdr.ethernet.ether_type) {
+            0x6666 : parse_reg;
+            default: accept;
+        }
+    }
+
+    state parse_reg {
+        pkt.extract(hdr.reg);
+        transition accept;
+    }
+}
+
+    /***************** M A T C H - A C T I O N  *********************/
+
+control Ingress(
+    /* User */
+    inout my_ingress_headers_t                       hdr,
+    inout my_ingress_metadata_t                      meta,
+    /* Intrinsic */
+    in    ingress_intrinsic_metadata_t               ig_intr_md,
+    in    ingress_intrinsic_metadata_from_parser_t   ig_prsr_md,
+    inout ingress_intrinsic_metadata_for_deparser_t  ig_dprsr_md,
+    inout ingress_intrinsic_metadata_for_tm_t        ig_tm_md)
+{
+    Register<bit<16>,bit<8>>(256,0)   reg_test1;
+    RegisterAction<bit<16>, bit<8>, bit<16>>(reg_test1) reg1_insert = {
+        void apply(inout bit<16> set_store){
+            set_store = hdr.reg.data;
+        }
+    };
+
+    RegisterAction<bit<16>, bit<8>, bit<16>>(reg_test1) reg1_read = {
+        void apply(inout bit<16> value, out bit<16> ret){
+            ret = value;
+            value = 0x0;
+        }
+    };
+
+    Register<bit<16>,bit<8>>(256,0)   reg_test2;
+    RegisterAction<bit<16>, bit<8>, bit<16>>(reg_test2) reg2_insert = {
+        void apply(inout bit<16> set_store){
+            set_store = hdr.reg.data;
+        }
+    };
+
+    RegisterAction<bit<16>, bit<8>, bit<16>>(reg_test2) reg2_read = {
+        void apply(inout bit<16> value, out bit<16> ret){
+            ret = value;
+            value = 0x0;
+        }
+    };
+
+    apply {
+        ig_tm_md.ucast_egress_port = ig_intr_md.ingress_port;
+        if(hdr.reg.opcode == 1){
+            if(hdr.reg.reg_choice == 1){
+                reg1_insert.execute(hdr.reg.reg_index);
+            }
+            else if(hdr.reg.reg_choice == 2){
+                reg2_insert.execute(hdr.reg.reg_index);
+            }
+            else if(hdr.reg.reg_choice == 3){
+                reg1_insert.execute(hdr.reg.reg_index);
+                reg2_insert.execute(hdr.reg.reg_index);
+            }
+        }
+        else if(hdr.reg.opcode == 2){
+            if(hdr.reg.reg_choice == 1){
+                hdr.reg.data = reg1_read.execute(hdr.reg.reg_index);
+            }
+            else if(hdr.reg.reg_choice == 2){
+                hdr.reg.data = reg2_read.execute(hdr.reg.reg_index);
+            }
+        }
+    }
+}
+
+    /*********************  D E P A R S E R  ************************/
+
+control IngressDeparser(packet_out pkt,
+    /* User */
+    inout my_ingress_headers_t                       hdr,
+    in    my_ingress_metadata_t                      meta,
+    /* Intrinsic */
+    in    ingress_intrinsic_metadata_for_deparser_t  ig_dprsr_md)
+{
+    apply {
+        pkt.emit(hdr);
+    }
+}
+
+
+/*************************************************************************
+ ****************  E G R E S S   P R O C E S S I N G   *******************
+ *************************************************************************/
+
+    /***********************  H E A D E R S  ************************/
+
+struct my_egress_headers_t {
+}
+
+    /********  G L O B A L   E G R E S S   M E T A D A T A  *********/
+
+struct my_egress_metadata_t {
+}
+
+    /***********************  P A R S E R  **************************/
+
+parser EgressParser(packet_in        pkt,
+    /* User */
+    out my_egress_headers_t          hdr,
+    out my_egress_metadata_t         meta,
+    /* Intrinsic */
+    out egress_intrinsic_metadata_t  eg_intr_md)
+{
+    /* This is a mandatory state, required by Tofino Architecture */
+    state start {
+        pkt.extract(eg_intr_md);
+        transition accept;
+    }
+}
+
+    /***************** M A T C H - A C T I O N  *********************/
+
+control Egress(
+    /* User */
+    inout my_egress_headers_t                          hdr,
+    inout my_egress_metadata_t                         meta,
+    /* Intrinsic */    
+    in    egress_intrinsic_metadata_t                  eg_intr_md,
+    in    egress_intrinsic_metadata_from_parser_t      eg_prsr_md,
+    inout egress_intrinsic_metadata_for_deparser_t     eg_dprsr_md,
+    inout egress_intrinsic_metadata_for_output_port_t  eg_oport_md)
+{
+    apply {
+    }
+}
+
+    /*********************  D E P A R S E R  ************************/
+
+control EgressDeparser(packet_out pkt,
+    /* User */
+    inout my_egress_headers_t                       hdr,
+    in    my_egress_metadata_t                      meta,
+    /* Intrinsic */
+    in    egress_intrinsic_metadata_for_deparser_t  eg_dprsr_md)
+{
+    apply {
+        pkt.emit(hdr);
+    }
+}
+
+
+/************ F I N A L   P A C K A G E ******************************/
+Pipeline(
+    IngressParser(),
+    Ingress(),
+    IngressDeparser(),
+    EgressParser(),
+    Egress(),
+    EgressDeparser()
+) pipe;
+
+Switch(pipe) main;
diff --git a/register_test/result.pcapng b/register_test/result.pcapng
new file mode 100644
index 0000000..78e33b1
--- /dev/null
+++ b/register_test/result.pcapng
diff --git a/register_test/send.py b/register_test/send.py
new file mode 100644
index 0000000..1369450
--- /dev/null
+++ b/register_test/send.py
@@ -0,0 +1,49 @@
+#!/usr/bin/python
+
+import os
+import sys
+
+if os.getuid() !=0:
+    print """
+ERROR: This script requires root privileges. 
+       Use 'sudo' to run it.
+"""
+    quit()
+
+from scapy.all import *
+
+class TnaReg(Packet):
+    name="TNA Register test"
+    fields_desc=[
+        StrFixedLenField('Name','Test',4),
+        StrFixedLenField('Op', 'Op', 2),
+        ByteField('Opcode', 0),
+        StrFixedLenField('Reg', 'Reg', 3),
+        ByteField('RegChoice', 0),
+        ByteField('Index',0),
+        ShortField('Data', 0)
+	]
+bind_layers(Ether, TnaReg, type=0x6666)
+
+
+print "Sending TnaReg packet to"
+p1 = (Ether(dst="00:11:22:33:44:55", src="00:aa:bb:cc:dd:ee")/
+     TnaReg(Op="w", Opcode=1, RegChoice=1, Index=5, Data=18))
+
+p2 = (Ether(dst="00:11:22:33:44:55", src="00:aa:bb:cc:dd:ee")/
+     TnaReg(Op="r", Opcode=2, RegChoice=1, Index=5))
+
+p3 = (Ether(dst="00:11:22:33:44:55", src="00:aa:bb:cc:dd:ee")/
+     TnaReg(Op="w", Opcode=1, RegChoice=2, Index=20, Data=288))
+
+p4 = (Ether(dst="00:11:22:33:44:55", src="00:aa:bb:cc:dd:ee")/
+     TnaReg(Op="r", Opcode=2, RegChoice=2, Index=20))
+
+p5 = (Ether(dst="00:11:22:33:44:55", src="00:aa:bb:cc:dd:ee")/
+     TnaReg(Op="w", Opcode=1, RegChoice=3, Index=10, Data=233))
+
+sendp(p1, iface="veth7") 
+sendp(p2, iface="veth7") 
+sendp(p3, iface="veth7") 
+sendp(p4, iface="veth7") 
+sendp(p5, iface="veth7")